EM78P159N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology. It is quipped with 1K x 13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits to prevent user's code in the OTP memory from being intruded. 8 OPTION bits are also available to meet user's requirements.
With its OTP-ROM feature, the EM78P159N is able to offer a convenient way of developing and verifying user's programs. Moreover, user can take advantage of ELAN Writer to easily program his development code.
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EM78P159N is an 8-bit microprocessor designed and developed with low-power, high-speed CMOS technology. It is quipped with 1K x 13-bits Electrical One Time Programmable Read Only Memory (OTP-ROM). It provides three PROTECTION bits to prevent user's code in the OTP memory from being intruded. 8 OPTION bits are also available to meet user's requirements.
With its OTP-ROM feature, the EM78P159N is able to offer a convenient way of developing and verifying user's programs. Moreover, user can take advantage of ELAN Writer to easily program his development code.
Features
Operating voltage range:?
* 2.1V ~ 5.5V at 0°C ~ 70°C?
* 2.3V ~ 5.5V at 40°C ~ 85°C
Operating frequency range (base on 2 clocks ):?
* Crystal mode: DC ~ 20MHz at 5.0V, DC ~ 8MHz at 3.0V, DC ~ 4MHz at 2.1V?
* ERC mode: DC ~ 4MHz at 5.0 ~ 2.1V?
* IRC mode: 4 choices of frequencies available; I.e., 8M, 4M, 1M, & 455KHz
IRC mode:?
* All these four main frequencies can be trimmed by programming with four calibrated bits in the ICE159N Simulator.?
?? OTP is auto trimmed by DWTR.?
* Temperature, Voltage, and Process changes will influence the frequency drift?
* Frequency deviation is only ±4.5% after auto trimming (based on Vdd=5V,Ta=25°C)
Fast set-up time only requires about 2ms in high XTAL and 32CLKS in IRC mode from wake up to operating mode
Low power consumption:?
* Less then 2mA at 5V/4MHz?
* Typically 20μA at 3V/32kHz?
* Typically 1μA during Sleep mode
1K x 13 bits on chip ROM
One security register to prevent intrusion of OTP memory codes
One configuration register to accommodate user's requirements
48 x 8 bits on chip registers (SRAM, general purpose register)
2 bi-directional I/O ports
5 level stacks for subroutine nesting
8-bit real time clock/counter (TCC) with selective signal sources, trigger edges, and overflow interrupt
Two clocks per instruction cycle
Power down (SLEEP) mode
Three available interruptions:?
* TCC overflow interrupt?
* Input-port status changed interrupt (wake up from Sleep mode)?
* External interrupt